Overview of Hardware Verification Technology

Our technology to functional verification of hardware designs is split into two verification approaches:

  • Unit-Level Approach

    is a specification-driven approach to automated testbench development for hardware design components (units) developed by means of HDL (Verilog, VHDL, SystemC, SystemVerilog, etc.). The approach uses cycle-accurate contract specifications in the form of pre- and post-conditions for description of design behavior and advanced FSM-based techniques for test sequence generation.

    The unit-level approach is supported by the CTESK tool.

  • Core-Level Approach

    is a model-based technology of test program generation for microprocessors and other programmable devices. The approach uses high-level instruction set descriptions for specification of microprocessor behavior and combinatorial techniques for test program construction.

    The core-level approach is supported by the MicroTESK tool.