Case Study on Hardware Verification


The approach to hardware verification presented here was used in several industrial projects on microprocessor verification at unit and core levels.

Practical applications of the unit-level approach are itemized below (see Unit-Level Case Study page for details):

 

  • verification of the translation lookaside buffer (TLB) (PDF file);
  • verification of the floating-point unit (FPU);
  • verification of the arithmetic-logic unit (ALU);
  • verification of the cache L2 (PDF file);
  • verification of the memory access unit hub (MAU-Hub);
  • verification of the north bridge data hub (DB);
  • verification of the interrupt controller (SAPIC);
  • verification of the traslation lookaside unit (TLU).

 

The following list contains applications of the core-level approach (see Core-Level Case Study page for details):

 

  • test program generation for the memory management unit;
  • test program generation for the MIPS64-compatible microprocessor (PDF file);
  • test program generation for the DSP coprocessor (PDF file);
  • test program generation for the arithmetical coprocessors (PDF file);
  • test program generation for the DMA controller;
  • test program generation for branch prediction unit.